High-frequency characterization of embedded components in printed circuit boards

The embedding of electronic components is a three-dimensional packaging technology, where chips are placed inside of the printed circuit board instead of on top. The advantage of this technology is the reduced electronic interconnection length between components. The shorter this connection, the faster the signal transmission can occur. Different high-frequency aspects of chip embedding are investigated within this dissertation: interconnections to the embedded chip, crosstalk between signals on the chip and on the board, and interconnections running on top of or underneath embedded components. The high-frequency behavior of tracks running near embedded components is described using a broadband model for multilayer microstrip transmission lines. The proposed model can be used to predict the characteristic impedance and the loss of the lines. The model is based on two similar approximations that reduce the multilayer substrate to an equivalent single-layer structure. The per-unit-length shunt impedance parameters are derived from the complex effective dielectric constant, which is obtained using a variational method. A complex image approach results in the calculation of a frequency-dependent effective height that can be used to determine the per-unit-length resistance and inductance. A deliberate choice was made for a simple but accurate model that could easily be implemented in current high-frequency circuit simulators. Next to quasi-static electromagnetic simulations, a dedicated test vehicle that allows for the direct extraction of the propagation constant of these multilayer microstrips is manufactured and used to verify the model. The verification of the model using simulation and measurements shows that the proposed model slightly overestimates the loss of the measured multilayer microstrips, but is more accurate than the simulations in predicting the characteristic impedance

Frequency-dependent substrate characterization via an iterative pole search algorithm

The characterization of frequency-dependent material properties is an important issue in nowadays high-speed interconnect design. This letter presents a practical method to determine the complex permittivity of a substrate material, by combining measurements with simulations. A rational permittivity model is determined by searching for its poles and residues using an iterative optimization method. Its accuracy is verified by comparing coplanar waveguide measurements with simulations based on the new material model

Flexible and stretchable circuit technologies for space applications

Flexible and stretchable circuit technologies offer reduced volume and weight, increased electrical performance, larger design freedom and improved interconnect reliability. All of these advantages are appealing for space applications. In this paper, two example technologies, the ultra-thin chip package (UTCP) and stretchable moulded interconnect (SMI), are described. The UTCP technology results in a 60 µm thick chip package, including the embedding of a 20 µm thick chip, laser or protolithic via definition to the chip contacts and application of fan out metallization. Imec’s stretchable interconnect technology is inspired by conventional rigid and flexible printed circuit board (PCB) technology. Stretchable interconnects are realized by copper meanders supported by a flexible material e.g. polyimide. Elastic materials, predominantly silicone rubbers, are used to embed the conductors and the components, thus serving as circuit carrier. The possible advantages of these technologies with respect to space applications are discussed

Embedded passive components for improved power plane decoupling

In this paper, a detailed power integrity study is described that compares the behavior of surface-mount devices and embedded components for power decoupling. Through measurements and simulations, it is found that when the layer count of the board is low, there is no significant difference between both technologies. When the number of layers increases, the short connection for the embedded components is clearly superior to the surface-mount capacitor. The resonance frequencies for the embedded capacitor do not change significantly with the increased layer count. The case with the surface-mount capacitor however, shows a large increase in parasitic inductance due to the long vias through the board

A modular and interactive OLED-based lighting system

The concept of a flexible, large-area, organic light emitting diode (OLED)-based lighting system with a modular structure and built-in intelligent light management is introduced. Such a flexible, thin, portable lighting system with discreetly integrated electronics is important in order to allow the implementation of the lighting system into a variety of places, such as cars and temporary expedition areas. A modular construction of an OLED lighting panel makes it possible to control each OLED cell individually. This not only enables us to counteract aging or degradation effects in the OLED cells but it also allows individual OLED module brightness control to support human or ambient interaction based on integrated or centralized sensors. Moreover, integrating the driving electronics in the backplane of an OLED module improves the energy efficiency of operating large OLED panels. The thin, modular construction and individual, dynamic control are successfully demonstrated

High yield fabrication process for 3D-stacked ultra-thin chip packages using photo-definable polyimide and symmetry in packages

Getting output of multiple chips within the volume of a single chip is the driving force behind development of this novel 3D integration technology, which has a broad range of industrial and medical electronic applications. This goal is achieved in a two-step approach. At first thinned dies are embedded in a polyimide interposer with a fine-pitch metal fan-out resulting Ultra-Thin Chip Packages (UTCP), next these UTCPs are stacked by lamination. Step height at the chip edge of these UTCPs is the major reason of die cracking during the lamination. This paper contains an approach to solve this issue by introduction of an additional layer of interposer which makes it flat at the chip edge and thus the whole packages is named as “Flat-UTCP”. In addition to that, randomness in non-functional package positions per panel reduces the overall yield of the whole process up to certain extent. A detailed analysis on these two issues to improve the process yield is presented in this paper. 3D-stacked memory module composed of 4 EEPROM dies was processed and tested to demonstrate this new concept for enhancing the fabrication yield

Accelerated hermeticity testing of biocompatible moisture barriers used for the encapsulation of implantable medical devices

Barrier layers for the long-term encapsulation of implantable medical devices play a crucial role in the devices’ performance and reliability. Typically, to understand the stability and predict the lifetime of barriers (therefore, the implantable devices), the device is subjected to accelerated testing at higher temperatures compared to its service parameters. Nevertheless, at high temperatures, reaction and degradation mechanisms might be different, resulting in false accelerated test results. In this study, the maximum valid temperatures for the accelerated testing of two barrier layers were investigated: atomic layer deposited (ALD) Al2O3 and stacked ALD HfO2/Al2O3/HfO2, hereinafter referred to as ALD-3. The in-house developed standard barrier performance test is based on continuous electrical resistance monitoring and microscopic inspection of Cu patterns covered with the barrier and immersed in phosphate buffered saline (PBS) at temperatures up to 95 °C. The results demonstrate the valid temperature window to perform temperature acceleration tests. In addition, the optimized ALD layer in combination with polyimide (polyimide/ALD-3/polyimide) works as effective barrier at 60 °C for 1215 days, suggesting the potential applicability to the encapsulation of long-term implants